The present invention concerns the prediction of the capacitance of connection nets after they are placed on an integrated circuit.
In integrated circuits, delay through a component is dependent upon the load the component is required to drive. The load a component has to drive is dependent upon the fanout from the output of the component and dependent upon the length of connection lines which are part of the output net of the component.
When designing integrated circuits, it is important in estimating performance of the integrated circuit to estimate the delay through components. After the logic of the circuit has been designed, and before the integrated circuit has been manufactured, it is possible to determine the fanout from each component. However, the length of the connection wires which form the output net of the component and the resulting interconnect capacitance of the output net are difficult to predict with accuracy.
Typically, in the prior art, this net capacitance has been estimated solely on the basis of fanout from the component and empirically determined constants. For example the following Formula 1 or other similar formulas are typically used to determine the interconnect capacitance of nets. EQU Capacitance=c.sub.1 +c.sub.2 *Fanout Formula 1
In the above Formula 1, Fanout is the number of components driven by the output of the component, Capacitance is the predicted capacitance of the output net from the component and c.sub.1 and c.sub.2 are constants which are determined from statistics of previously routed designs. Besides using a straightforward formula as Formula 1 above, some attempts have been made to use more elaborate procedures to calculate net capacitance based on fanout. Such procedures generally use tables which indicate statistically typical values for capacitance as a function of fanout. Some tables take into account floor planning information available at the time the prediction is made.
One problem with the prior methods of predicting the capacitance of nets is the wide variation in the actual value of the capacitance of nets. For example, for most output nets with a fanout of 1, the connection lines are short and so the capacitance of the net is low. However, a small number of nets have much longer connection lines and thus much greater capacitance. If standard statistical techniques are used to predict capacitance of output nets, most of the nets will have less capacitance than the predicted value, while a small number of the output nets will have a capacitance which is several times greater than the predicted value. If one or more of the output nets with significantly greater capacitance is on a circuit path which is critical to performance, then the performance of the integrated circuit may be less than predicted. Such impaired performance of all or a section of an integrated circuit could require a designer to manually re-route connection lines in an integrated circuit. In some cases, it is required to redesign the logic of the integrated circuit.
One way to avoid the problem of significantly underestimating the capacitance of nets of some components is to simply predict much larger capacitance for all nets. This would guarantee that the predicted capacitance would be much closer for those few components with nets having significantly greater capacitance. However, using such inflated predictive values would generally result in underestimating actual performance of the integrated circuit.